1. Technical Field
The present disclosure relates to the field of wireless communications, and more specifically aims at methods and devices for transmitting radio frequency signals.
2. Discussion of the Related Art
FIG. 1 is a simplified block diagram of a radio frequency signal transceiver device 100 where the processing of the radio frequency signals is of essentially digital nature.
Device 100 comprises an antenna 102 and a digital signal processor 104 (DSP) for example comprising a microprocessor. In the receive direction, the analog signal received by antenna 102 crosses a low-noise amplifier 106 (LNA), and is then directly converted into a digital signal by an analog-to-digital converter 108 (ADC) having its output connected to an input of digital processor 104. The basic signal processing operations, and especially carrier demodulation operations, are digitally carried out by device 104. In the transmit direction, device 104 directly generates a digital signal having the shape of a carrier wave modulated by the data to be transmitted, ready to be transmitted over the network. This signal is simply converted into an analog signal by a digital-to-analog converter 110 (DAC) placed at the output of device 104, and then amplified by a power amplifier 112 (PA), before being transmitted by antenna 102.
This type of device is sometimes called “radio software” since the processing implemented by the receiver and by the transmitter are essentially software in nature.
An advantage of such a device is that it is sufficient to reprogram the software part to make the device compatible with new communication standards (new carrier frequencies, new modulations, etc.).
However, in practice, the use of transceiver devices of purely software nature often may not be considered since this may require extremely fast converters and a digital processor capable of providing considerable computing power. Indeed, present communication standards use carrier frequencies on the order of a few GHz. To be able to process such signals in real time, the bandwidth of the converters and of the calculation device should be at least equal to 10 GHz. Further, to have satisfactory signal quality, a sampling over at least 16 bits should generally be provided. Converters and calculation devices capable of fulfilling such constraints have a considerable power consumption, conventionally ranging from 500 to 1,000 watts. Such a power consumption is incompatible with most network devices, and in particular with portable terminals.
FIG. 2 is a simplified block diagram of a radio frequency signal transceiver device 200, illustrating a solution which has been provided to decrease the constraints on converters and on the signal digital processor.
On the receive chain side, device 200 comprises the same elements as device 100 of FIG. 1, and further comprises a device 202 (SASP—Sampled Analog Signal Processor) for pre-processing the analog signal, arranged between the output of low-noise amplifier 106 and the input of analog-to-digital converter 108. Device 202 is configured to perform an analog pre-processing of the signal, enabling to lower the operating frequency to be able to return to conditions compatible with low power consumption conversion and digital processing devices. Functionally, device 202 selects a frequency envelope (or several envelopes in the case of a multistandard terminal) of the signal received by antenna 102, and lowers the frequency of the signal contained in this envelope. To achieve this, device 202 comprises a sampling circuit capable of delivering analog samples of the input signal, and a processing circuit capable of performing a discrete Fourier transform processing on the signal samples and of delivering first intermediate analog samples. Device 202 further comprises a processing circuit capable of modifying the spectral distribution of the first intermediate samples and of delivering second intermediate analog samples, and a processing circuit capable of performing an inverse discrete Fourier transform on the second intermediate samples and of delivering analog samples of an output signal having a lower frequency than the input signal. Detailed examples of embodiment of device 202 are described in patent application WO 2008/152322 and in article “65 nm CMOS Circuit Design of a Sampled Analog Signal Processor dedicated to RF Applications” by François Rivet et al.
The receive chain of device 200 has the advantage of providing a particularly advantageous rapidity and consumed power saving, especially in mobile telephony applications, while allowing a multistandard use and being easily reconfigurable in case of a modification of a communication standard or in case of the occurrence of a new standard.
On the transmit chain side, device 200 comprises conventional means for modulating a carrier signal with digital data. In the shown example, device 200 can alternately or simultaneously transmit data on two carrier waves P1 and P2 having different frequencies. Carrier signals P1 and P2 are respectively generated by a wave generator 204 and by a wave generator 206. Each wave generator for example comprises a voltage-controlled oscillator controlled by a quartz. A first modulator 205, for example comprising a multiplier, receives on the one hand signal P1 provided by generator 204, and on the other hand a bit train D1 of data to be transmitted provided by digital processor 104. Modulator 205 generates a signal P1′ corresponding to carrier P1 modulated by data D1 to be transmitted. A second modulator 207, for example comprising a multiplier, receives on the one hand signal P2 provided by generator 206, and on the other hand a bit train D2 of data to be transmitted provided by digital processor 104. Modulator 207 generates a signal P2′ corresponding to carrier P2 modulated by data D2 to be transmitted. Signals P1′ and P2′ are added by an adder 208, and the resulting signal is amplified by power amplifier 112, and then emitted by antenna 102.
The transmit chain of device 200 is fast and saves consumed power but has the disadvantage of not being easily reconfigurable in case of a modification of communication standards or in the case where new standards appear.
In the example of FIG. 2, the transmit chain of device 200 further comprises a counter-feedback loop enabling to verify that the signal transmitted by antenna 102 comprises no error. The counter-feedback loop comprises a coupler 210 which samples part of the output signal of power amplifier 112 (signal transmitted by antenna 102). The signal sampled by coupler 210 crosses a low-noise amplifier 212 (LNA) and a demodulation and digitization circuit 214. The digitized signal provided by circuit 214 is sent to digital processor 104, which verifies whether the signal actually coincides with that which was desired to be transmitted.
The provision of the counter-feedback loop, which actually corresponds to a simplified receive chain arranged in parallel with the main receive chain, has the disadvantage of increasing the bulk, the cost, and the power consumption of the device.
Another disadvantage is that circuit 214 generally comprises, for each communication standard capable of being used in transmit mode, a specific analog hardware demodulator. Circuit 214 is thus not easily reconfigurable in the case of a modification of communication standards.